This project's funding goal was not reached on October 21, 2012.
About this project
The mathematics below shows how up to six digits of precision are derived. The system is driven by a 125 MHz crystal oscillator. The clock source being measured is the frequency of an Accutron Watch, which oscillates around 360 Hz. For each cycle of the Accutron Watch frequency, approximately 347,222 counts are counted by a high-speed 24-bit counter driven by the 125 MHz oscillator. Two high-speed 24-bit counters are used to capture each cycle of the Accutron Watch. Every cycle of 24-bit counter data is then captured and sent serially over the USB Port to a notebook computer where the raw counter data is analyzed and displayed.
The waveforms diagram below shows various testpoints indicted in the System Diagram above. It shows how each cycle of the Accutron Watch is captured and digitized with ultra-high precision.
Shown below is an electronic schematic prototype design I plan to implement. To detect the vibration of the tuning fork Accutron Watch, a magnetic induction coil is used. The detected oscillation is signal conditioned as the first stage of the Timing Processor. Two modes are provided. The Standard Mode (STD_MODE) features a filtered input designed to properly condition the frequency coming from the Watch and remove extraneous noise that may interfere with the timing. The Mumford Mode (MUM_MODE) is a special request that provides an input emulation of a previous generation device. Switch SW1 allows selection between these two modes of input conditioning. Both modes provide a positive square wave signal to the LC4256ZE Complex Programmable Logic Device or CPLD made by Lattice Semiconductor. The CPLD contains the necessary hardware and switching speed to measure the frequency of the Watch and package this frequency for transmission over a USB Port to a Notebook Computer.
Detailed below shows how the CPLD is connected to an off-the-shelf USB Interface called FT2232H Mini Module. This Module contains the necessary circuitry to properly interface to the high-speed USB 2.0 Port. Also provided is another USB port, which is used program the CPLD. This Port is built into the CPLD Breakout Board.
The software tools for developing the CPLD configuration pattern is available free of charge from Lattice Semiconductor. Verilog is the hardware programming language.
Shown below is software running on a Notebook Computer will receive captured raw packets of 24-bit counter information. The information is being received at a rate of around 360 packets / second over the USB 2.0 Port. The software can apply special filtering algorithms that will smooth out the waveform allowing a temporal shift to be easily observed. For more information about research applications, please visit: http://SmartWATCHSystem.com
Risks and challenges
1. This project involves completing the prototype and testing the prototype.
2. Software must be written and tested for the prototype. 1st release of the software shall run on a Windows XP system.
3. Design a PC board version.
4. Assemble and test the PC board.
5. Build and test PC boards for customers on Kickstarter.
6. Deliver PC board version with software to customers.
Have a question? If the info above doesn't help, you can ask the project creator directly.
- (30 days)