We integrate MAX10 2K-LE 10M02SC-U169 model
(for MAX10 specs, please refer to:
1. IN THE FUTURE, user will be able to upload custom fw inside the FPGA; IN THE FUTURE, we will open a special section on UP-community but today there is no plan on when this will be done. We cannot do it immediately as in case of wrong design, the board could be damaged so we have first to find a "safe-design-flow"
2. CPU is connected to FPGA by following ports: UART, 4x I2C, I2S, SPI (up to 3 SPI ports for specific models), 2xPWM, 2xOSCILLATOR, 10x GPIO, SDIO3.0, LPC, CPU-wakeup
3. FPGA pin are directly exposed on legacy HAT_connector (40pts header) and -new- EXHAT_connector which is HIROSE hi-speed mode. On EXHAT_conn the FPGA provides LVDS hi-speed bus 8 diff-pair +PLL_IN diff-pair +PLL_OUT diff-pair (all this can be used as GPIO if there is need of LVDS bus) while CPU provides USB3 port, UART port, 2x I2C
4.the EMIF is not supported on MAX10 U169, it is supported starting from MAX10 16K F256 / U324 packages (much more expensive); we could support this for Custom industrial projects only (10k pieces MOQ; contact email@example.com); FPGA has small internal memory of 108kb for 2K LE version. The only way I see to "simulate" a memory access for FPGA is thru a SDIO3.0 port (800Mbps bandwidth) whereas FPGA application generates and IRQ request asking the CPU to read/write (map) some LPDDR4 MEM-pages onto FPGA internal MEM ... latency would be low, but SDIO3.0 BW would be enought ... writing this application would require access to SDIO3.0 slave and a lot of work.
5. The board will be shipped with a defaul FPGA-fw enabling the legacy HAT-conn functions and EXHAT functions as GPIOs-only; IN THE FUTURE we will provide new functionalities but there is no plan yet on when this will be done.
6. FPGA fw update will be done safetly under OS; no need to use cables, it is same procedure of a standard BIOS update.
7. we will provide UP2 with MAX10 of 4K LE, 8K LE and 16K LE at higher cost; today there is no plan on when this will be done
8. in general WE ARE IN FAVOUR of cooperating with MAKERS to develop FPGA custom design; but we have to do this SAFETLY as RTL design is a complex task which could damage the board.