Complete Verilog implementation of a 2D/ 3D graphics processor capable of OpenGL and D3D w/ full test suite Read more
This project's funding goal was not reached on on .
About this project
Help fund us to create the the first professional quality Open Source GPU and help Kickstart an Open Hardware revolution. The current aim is to finish the final few modes of operation and release our product as a complete, professional, open source hardware platform. We will provide a complete Verilog implementation of a 2D/3D graphics processor capable of OpenGL and D3D with a full test suite that anyone is free to use and improve upon. Our Ultimate stretch goal is to create a complete open source implementation of a modern day graphics accelerator.
History/ About Us
Our company Silicon Spectrum was founded in 2002 at the request of numerous former Number Nine Customers who were no Longer able to purchase Number Nine Graphics Accelerators. Rather than trying to start from scratch, we licensed and re-implemented the same graphics technology that we had developed for Number Nine and optimized it for use in an FPGA creating a graphics accelerator compatible with the #9 Ticket To Ride IV. The reason behind this was to provide a binary compatible graphics core for vertical markets: Medical Imaging, Military, Industrial, and Server products. Our 2D/ 3D implementation, has since also been used in Digital picture frames, Avionics equipment and on a range of FPGA based products. Now we are running a Kickstarter to finish the final few modes of operation with the goal of a complete, professional, open source hardware platform.
How do you Open Source GPU (Hardware)?
We will release a Verilog implementation of a GPU under the LGPL open source licence. We would like anyone be able to use it. Want to link it with an ARM? Go right ahead. Want to do a complete open source SOC? Go ahead. But if you modify it, you have to make the modifications available. If you leave it alone, you just need to provide the source.
What is Verilog?
Verilog is a description language commonly used in the design and verification of digital circuits.
How does it work there are no pledges to buy the GPU hardware?
The goal of this project is to provide the hardware design for use by anyone who wants to use it to create an ASIC GPU. The Verilog can also be used to run the GPU in reprogrammable chips called FPGA's. These chips allow you to make numerous changes (tinker with) the GPU design without the need to produce expensive hardware and can be purchased off the shelf so they are great for those interested in hardware design or playing with this technology. The downside is these chips are generally slower than a common non-reprogrammable ASIC implemented GPU's.
Why should I support this?
Computer software is currently advancing at a phenomenal rate and at the heart of many new innovations in software is Open Source. We want to Kickstart a revolution in the computer hardware industry and make Open Hardware a reality. Our GPU is never going to compete with a Nvidia or AMD GPU from the word go, but its a start towards a future with open hardware,10 years from now our GPU could look very different. Linux itself started off as a small project well behind the Unix's of the day, now the Linux market dwarfs all the Unix's combined.
Goal and Stretch Goals
We have broken down the design into the following Goals:
$200,000 Fully Funded - 2D only
This is our goal in which we will release a 2D only core containing a PCI interface, CRT controller (to drive a monitor utilizing a DVI/ HDMI chip or DAC), 2D accelerator supporting lines, solid fills, patterned fills and bit BLTs. It also has a fully IBM compatible VGA controller for legacy operations.
We will also commit to a simple bus interface design to be released in the future (Q2 2014) that will allow easy connection to an Arduino, Raspberry-Pi, Altera/Xilinx SOC or PCIe core.
This and all goals contain a testbench with numerous tests to simulate modes of operation.
$400,000 3D Option
This Stretch Goal adds optional* full OpenGL and Direct 3D (7.0/8.0) 3D graphics.
(*) The 3D can be left out to save space if 2D is all that is required.
- Single pass nearest or bilinear filtering.
- Two pass Trilinear
- Mip mapping
- Specular lighting
- Gouraud Shading
- Alpha blending and compare
- Z buffering
- Area pattern
- Color expansion
- Stipple mode
- 3D color keying
- Backface culling
- Triangle setup
This tier is currently undergoing bug fixing and we anticipate delivery Q1 2014.
$600,000 Performance improvements
The design has been optimized for current technologies, but it is missing some features (Bump Mapping, texture compression, higher speed, single pass trilinear) This tier will address that.
This is new design work and our anticipated delivery would be Q3 2014.
$1,000,000 Universal Shader
This is our ultimate stretch goal and requires a complete redesign. It's something we have been wanting to do for years, but didn't have the resources. This would allow us to create a complete open source implementation of a modern day graphics accelerator.
If we receive more than the above, it will allow us to devote more time and effort to the project and we'll be able to release code sooner.
This is new design work and our anticipated delivery would be Q2 2015.
Licensing and Deliverables
This is where we believe we are unique. Our deliverables are Verilog source code and testbenches. They will run on modern simulators and the design has been tested in both Altera and Xilinx. Unlike other open source hardware projects, you will have access to everything, including board design files for the 2D part. (3D would require rework).
Our licensing model is LGPL v3 as we treat this almost like a software linked library. If you improve or modify our code, it must be released under the LGPL v3 or later license. However, you are free to use the design as part of a larger design or system as long as you comply with the LGPL v3 or later.
Dec 2013 - GPU will start propagating to our SVN server for Beta Access backers. This will be 2D. (3D should the stretch goal be met).
Feb 2014 - Source will be frozen and 3 month early access backers will get access to our SVN server. USB keys will go out to Beta and Early access backers.
May 2014 - General release. SVN will be open to the world and remaining USB keys will ship.
Q2 2014 - Should our stretch goal be met, generic Interface support will be added and released in the SVN.
Q3 2014 - Should our stretch goal be met, additional features and performance enhancements will be released into the SVN.
Q1 2015 - Should our ultimate stretch goal be reached, the Unified Shader Model SVN will be opened to beta access backers.
Q2 2015 - Should our ultimate stretch goal be reached, the Unified Shader Model will be released to early access backers.
Q3 2015 - Should our ultimate stretch goal be reached, the Unified Shader Model will be released to the public.
Risks and challenges
Risks for the 2D core are mostly non existent. We need to polish the code and documentation, then release.
The 3D core has a few missing features we need to complete and will have a Q1 2014 release.
The AXI interfaces and above are new code. We are intimately familiar with the design and have over 20 years of ASIC and FPGA experience each. We anticipate a Q2 2014 release.
Software drivers are a challenge, and we will work on providing some level of drivers, with the hopes that the community takes them up and pushes them to new levels and provides problem reports to us.
Some questions have come up regarding patents. I think we are safe in the lower tiers as the technology is 15+ years old and we knew of no patents and no patent lawsuits were filed against us at #9.
That said, the Unified Shader may pose challenging, but I would think any existing patents would be based on ways of doing things and we can work around them. We would be following OpenCL, as far as I understand an open standard.
This is an error on my part. The USB key will ship to international backers also. I'm sorry for the confusion.
An FPGA is a Field Programmable Garte Array. This is a chip which you can write code for (VHDL or Verilog) and compile it (Synthesis) which turns it into an actual hardware design based upon boolean logic, Flip Flops, Ram and higher level functions. These are configurable pieces of hardware that these days can be developed upon by anyone. The tools for smaller designs are free, and the development hardware moderately expensive.
An ASIC is a fixed chip which is developed much like an FPGA, but it doesn't have the overhead of an FPGA. This means it is faster, but orders of magnitude more expensive since it requires tools and actual fabrication. The mask set is typicallt the most expensive part and you get one shot to get it right. New masks can run > $1 Million.
The GPU isn't meant to compete with the likes of Nvidia or AMD. Our current markets are ones where graphics cannot change every year/ 18 months. It costs more to re-certify software than to replace an existing card with an FPGA based solution.
What the design is good for is for embedded systems. The design is small and the performance good enough for mobile applications. It also gives Arduino or Raspberry-Pi developers a display capability using an FPGA daughter card such as those by: http://papilio.cc/
The code is readily targeted towards FPGAs. There are many development boards available from Altera and Xilinx that could be used to develop either PC graphics cards or Embedded devices. Some even have LCD screens you could drive directly. We will be releasing a generic interface version with the lowest tier, so with minimal effort, you could target just about any CPU.
Altera PCIe for 2D/3D More then enough power: http://www.terasic.com.tw/cgi-bin/page/archive.pl…
Altera Embedded SOC (ARM + FPGA) for 2D/ 3D: http://www.terasic.com.tw/cgi-bin/page/archive.pl…
Xilinx Embedded (2D/ 3D): http://zedboard.org
We are also exploring other options:
Adapteva: http://www.adapteva.com. They have a Zynq 7010/20 which can handle the 2D easily 3D with some work.
Arduino: http://papilio.cc - an FPGA daughter card for the Arduino. We are in the process of contacting them to determine if they can place a larger FPGA on their board.
Raspberry Pi: A few options are available that we are exploring.
Drop us a line if you'd like to know about your favorite platform
Short answer: Your best bet is to use the free simulator: modelsim-altera or xilinx isim.
Long answer: The code for the design will likely run in Icarus Verilog or Verilator. It's the test bench that is the problem. Typically the free simulators only handle synthesizable code. Verilator can use SystemC as a test environment, however, all our test code is Verilog. The biggest hurdle is that many FPGA components (the Memory controller for example) are typically encrypted and Verilator and Icarus don't handle that.
We run the 3D part in modelsim for altera without issue. It's a little slow, but it works.
Here is the latest build results for the fully loaded part w/ PCI.
This has signal tap in it, so the actual design is somewhat smaller.
1 ALM is 2 ALUTs, approximately equivalent to a LUT or LE, but in older technologies, there was only one Flip Flop per LUT/LE. Thus it's complicated without re-targetting.
Internal BIOS (For VGA) - ALM: 53, M9K: 32, DSP: 0
Clock Generator - ALM: 128, M9K: 1, DSP:
DDR3 Interface (Altera Component) - ALM: 2770, M9K: 19, DSP:
Drawing Engine (2D/3D) - ALM: 26873, M9K: 53, DSP: 253
Drawing Engine (2D only) - ALM: 3612, M9K: 15, DSP: 4
Display List Processor (DLP) - ALM: 463, M9K: 4, DSP:
Host Interface (PCI + Memory Windows) - ALM: 1800, M9K: 10, DSP:
Memory Controller Front End - ALM: 2688, M9K: 22, DSP: 50
(Blending, ROPs, arbitration)
MC Cache - ALM: 581, M9K: 8, DSP:
CRT (1 per display) - ALM: 719, M9K: 15, DSP:
RAMDAC (1/ display) - ALM: 1002, M9K: 9, DSP:
VGA (Only needed for legacy PC operations) - ALM: 1184, M9K: 4, DSP:
3D part total: ALM: 36600, M9K: 193, DSP 18x18: 303
2D part total: ALM: 13339, M9K: 155, 54.
Our eternal thanks for helping us complete and open the source for the community.Estimated delivery:
Your name on the list of backers on our website.Estimated delivery:
Your name on the list of backers in the specification.Estimated delivery:
A USB key with the source code when released. The delivery date will depend on whether this is part of an early access or not.Estimated delivery:Only ships to: United States
A USB key with the source code when released. The delivery date will depend on whether this is part of an early access or not.
(I goofed earlier and had the USB key only going to the US, regardless of which $100 option you choose, you'll get a key)Estimated delivery:Ships anywhere in the world
Early access to the source code.
We will provide early access (approx 3 months) to this level of backer. This includes the USB key with the source.Estimated delivery:Ships anywhere in the world
We will provide access to the code as it is committed to the repository. This includes the USB key with the source in Feb 2014.Estimated delivery:Ships anywhere in the world
One of us will fly out and provide one day of training to the backer. The backer will need to provide a compatible simulator if you would like to run the code.
This Level of support includes the USB Key to ship in Feb 2014.Estimated delivery:Only ships to: United States
- (45 days)