heptane high performance OSS friendly CPU
heptane high performance OSS friendly CPU
A 9-issue VLIW cpu with out of order execution.There will be a 75%-80% native speed x86/x64 translator and Open Source firmware version
A 9-issue VLIW cpu with out of order execution.There will be a 75%-80% native speed x86/x64 translator and Open Source firmware version Read more
About this project
The heptane computer processor is a project to create a very fast computer processor in verilog harware description language, which will execute 9 instructions per clock cycle (as oposed to 4 by famous big company) and will run at above 2GHz if implemented on a modern chip process. It will be designed with ease of translation to x86/x64 arhitecture, and have about 80% native performance software translator for it. It will target the x86/x84 market via translation and also will feature native mode operating systerms. In practice, it could be used for: High performance x86_64 tablet (single core). High performance x86_64 laptop (dual core). Desktop x86_64(quad/six core). Servers and cloud (native and x86_64).
The Verilog HDL for the Processor is not yet ready, but the reservation stations and register files are done. More than half of the frontend is done. Register Alias Table is done. A previous version I was making, wich was 6 issue only, was ready enough to do multiple nested loops with dynamic branch prediction (no memory load/stores though). And then i decided to change it to 9 issue CPU. The L1 caches are already partially implemented.
The goal of the funding is to get the CPU to a working condition in the simulator, i don't promise to actually produce it with this amount of cash. Instead, i will try to find companies who might want to license it.
The CPU fetches 2 256 bit words in 1 clock, 6 instructions each, but only 9 go to the backend.All x86/x64 addressing modes will be supported without extra computation, except 64 bit absolute, as long as flat memory model (no segmentation) is used.
32 bit immediate opertands are supported (64 bit immediate mov takes 2 instructions).
With regards to the x86/x64 translator, one might think that it'll be slow, because previous attempts have been made to use a many instruction processor to emulate it and it was slow. However, the transmeta 8 instruction processor was in-order, had only 2 arithmetic-logic units and 2 load-store units. The heptane processor will have 3 load units, 2 store units, 6 arithmetic logic units and will feature out-of -order execution. The two processors aren't comparable.
On the floating point side - 4 128bit Floating Point Units - 2 add and 2 mul/fma. Will support up to avx2 instructions in the vm (combining pairs of 128 bit units into 256 bit one).
Integer simd - 4 128 bit integer units all supporting alu instructions (paired for 256-bit instructions). Avx2 support in VM (but without AESNI).
Please note that the old 6 issue backend has been verified by one program only and hasn't been extensivelly tested. The program's basic blocks were all less than 6 instructions, so it doesn't fully utilise the issue width(video of test included).
Apart from all this, I promise if I get funded that I will release the parts of the native firmware and the x86/x64 translator under open source license. However I will also offer proprietary version to customers so they are free to not release the code of their own parts.
Risks and challenges
After i get funded i will apply for 2-3 international patents and proceed with development. After it's complete, i'll offer it to companies to produce their own SOCs or processors. In order to test functionality, i'll rewrite some (heavily multiported) data structures to use timed multiplexing with multiple clock cycles and synthesise the Processor on one or more FPGAs. I'll also write a x86/x64 VM to test for running low-spec linux and/or old windows on it. I'll also do feature incomplete port of GCC (it's very similar to x64).
If I get customers for the VM +CPU combination or sufficient extra funding I'll do (not on my own, of course) a fully featured GCC & linux kernel port. Most applications for linux should compile fine if they do on x64. Even x64 inline assembly can work but might not fully use the features. The ones that don't run can be run on x86/x64 VM (both user mode and whole system emulation supported).
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