FPGA based multiple I/O port shield for any I2C bus. Ready to use, or develop your own control logic with free VHDL/Verilog software. Read more
This project's funding goal was not reached on July 10, 2013.
About this project
Now available for purchase on trifdev.com
A big THANK YOU to all our backers.
Unfortunately this project did not reach its target, and without this we did not have a sufficient quantity for a full production run. BUT, I will hand build as many boards as you want, so please visit trifdev.com where you can purchase blank boards or full assemblies. The tutorials and other information will be updated from time to time, so please check the web site for more information.
A special thank you to all those who gave helpful advice and suggestions for improvements. We will take those on to the next project!
UPDATE 1. The first pre-production board is now fully assembled and tested.
UPDATE 2. The schematics are now available on the trifdev.com web site.
UPDATE 3. The hardware description is now available on the trifdev.com web site.
UPDATE 4. The first production batch of pcbs is now on order, ahead of schedule.
UPDATE 5. Parts list and Gerber files released on trifdev.com
UPDATE 6. Look on the download page of the website for the Diamond constraint (*.lpf) file. This is one of the files required for compiling the FPGA code. It maps the logical name of each input/output function to its physical pin number. Also included are comments which identify the connector position for each pin.
UPDATE 7. The first Verilog file is now available on the trifdev.com web site. It is used to compile the I/O expander code loaded into the Trifdev FPGA board.
So what's it for?
Arduino boards are great, but sometimes you need more I/O pins, or maybe there is some time critical function which simply isn't achievable in software. This is where you need a FPGA (read on if you don't know what this is), but they have a reputation of being difficult to use, expensive and generally troublesome.
So how does this board solve the problem?
This is where this project can help. The board is supplied ready loaded with a simple I/O expander, which works straight out of the box to give you 58 more I/O pins. No FPGA programming required! Below is an example of the Arduino code needed to set the value of some FPGA I/O pins. Simple!
But it does more!
When you have tried the pre-loaded FPGA code, you could use it as a basis to develop your own functions, using FREE design software direct from the FPGA manufacturer. Maybe re-allocate the I/O pins, or add some extra logic to pre-process the incoming data, or include logic for controlling a specific device.
Give me some example applications!
- Complex I/O decoders
- Replace a whole collection of simple gates
- Make a motor controller
- Add specialised or extra UARTs
- Design your own CPU
- Implement fast algoithms, e.g. FFT
- And reprogram it time and time again
What is an "FPGA" anyway?
It stands for Field Programmable Gate Array. It is an integrated circuit which has a large number of very simple hardware functional blocks. When programmed, these blocks are interconnected, inside the device, to make up an electronic circuit.To create these interconnections, you use a programming language specially designed for this type of device. There are two such languages in common use, VHDL and Verilog. They both do much the same thing, and both are supported by TRIFDEV. The most important difference between these languages and a software language such as "C", or Arduino sketches, is that you are programming the hardware directly, by connecting gates, flip-flops, memory and so on. So when you read the code, it doesn't follow one step after another, but everything happens simultaneously. This is what makes FPGA designs so powerful.
But I don't understand how to write FPGA code!
We will show you how to download and run the software, and give some ready-made examples. All our code will be made available for you to use, and we will provide tutorials to explain how to modify it. It's always easier to start with something which works and adapt it, rather than starting from scratch. We don't pretend to be experts in VHDL or Verilog and our tutorials will be simple, but if you need more advanced information we will point you towards the many examples available on the web for you to gain a deeper understanding.
For some simple examples of VHDL code, see http://downloadsourcecodes.com/vhdl
Give me details!
The FPGA we use is a MACHXO2-1200, which has 1280 Look-Up-Tables (LUTs) so is capable of running quite complex functions. There are several built-in functions, including a programmable oscillator with PLL (0.024 – 400 MHz), I2C and SPI ports and a timer/counter. There is user RAM (64k bits) and user Flash (64k bits) to store variables and fixed parameters. All these are in addition to the LUTs. If you are a real hardware techie, there is logic analyser code which lets you see exactly what is going on inside the FPGA.
The board includes two push buttons and five LEDs, preconnected to the FPGA, which are useful for simple tests and for checking that the FPGA code is working. There are three extra 0.1" pitch sockets on the board, connected to free pins on the FPGA. The first has 21 I/O pins and 4 ground pins. The second connector has13 I/O pins alternating with ground pins for high speed signals. The third connector has 24 I/O pins. The standard Arduino connector holes are present, but the only connections are for power and the I2C bus, so this board does not interfere with any other shields.
The FPGA runs at 3.3v, so there is a voltage regulator on board. The power source can be either from the host Arduino, or from a USB connection, or from any other 5v supply. If the board is used stand-alone, it can supply 5v or 3.3v to other devices you may wish to connect, subject to maximum current limits of course.
The FPGA is programmed via a simple USB cable, using the free software downloadable from Lattice, the FPGA manufacturer.
There are more technical details on our web site www.trifdev.com .
Can I connect it to my Raspberry PI?
Yes, in principle you can connect it to almost any CPU. TRIFDEV has a standard I2C slave port, so you can easily connect it to any system which supports the I2C protocol. Even if the CPU doesn't directly support I2C, you can use a software "bit banging" method. It's beyond the scope of our tutorials, but a quick web search will provide examples.
Of course, the FPGA is re-programmable, so you could change it to incorporate one or more UART modules to implement serial ports if I2C is not convenient.
What else can it do?
This design has multiple possibilities:
- Use it as delivered to add extra input and output capability to an Arduino, or any other device with a I2C port. Just connect and go.
- Re-program it to include your own special functions. The programming software is a free download from Lattice, and all you need to add is a standard USB cable. No programming hardware required!
- Use it stand-alone, no processor needed. You can also add Arduino shields to enhance its function.
- Use it as a development platform as a quick start to your own design.
- Or as an educational tool.
Just remember that the FPGA is a 3.3v device; connecting its I/O pins to 5v without suitable protection may damage it.
All this is too simple, I'm a power FPGA user!
How about programming the FPGA to perform the Fast Fourier Transform algorithm, or implement your own CPU design, or a specialised UART? It might look simple, but you can use this board to develop highly complex functions.
Do you have prototypes yet?
A first prototype is already working, with simple VHDL code examples, both as a stand-alone board and controlled from an Arduino via the I2C port.
The pre-production batch is being tested right now.
The aim of this project is to finalise the production version of the board, and introduce it to potential users.
Will you release the hardware design?
Yes, if this Kickstarter project is fully funded, we will release the circuit diagrams and pcb layout. We have used DesignSpark for this project, as this is a free schematic capture and pcb layout package, supported by RS. (See http://www.designspark.com/ for further information.) So anyone can take our design and tailor it to suit their needs.
Our production plan.
TRIFDEV will be made in the UK. That is to say that the final assembly onto the pcb will be done in the UK. As with any electronic device, the individual components will be sourced from various parts of the world.
- First protoype build and test: Completed May 2013.
- Second prototypes and pre-production batch: In progress
- Kickstarter launch: mid June 2013
- Kickstarter end: mid July 2013
- Order production batch: end July 2013
- Despatch early-bird rewards: early August 2013
- Receive and test production batch: end August 2013
- Deliver all other rewards: September 2013
How do I get one?
Please become a backer! We need your help to launch the board into production, and look forward to sending you your reward.
Risks and challenges
The first prototypes are working well, and the pre-production version pcb has been tested. The web site is up and running with preliminary content. The I/O expander code is working and one other simple FPGA code example has been tested. While the Kickstarter project is running, we will develop the tutorials and further FPGA code examples.
Sub-contract assemblers have been identified, quotes obtained and costs have been established.
We have planned for a minimum production run, and also for up to 10 times this quantity. However, depending on the number of backers, there may be problems in component supply and logistical difficulty if we are overwhelmed with orders. If this happens we may have to switch to alternative suppliers, which could delay delivery of the rewards. We are confident that we can handle any reasonable quantity, but the risk is there. We promise to keep you all informed whatever happens.
Thanks for reading to the end!Learn about accountability on Kickstarter
It's not a simple answer. The main logic elements are Look Up Tables, (LUT4) of which there are 1280. Each LUT4 takes up to 4 inputs and a "carry" bit and produces an output which can be any logical function of the inputs. So it doesn't translate directly into a gate count.
In addition, there are several "hardened functions" comprising I2C, SPI and Counter/Timer blocks. There is also an oscillator, PLL, 64k bits of SRAM, 10k bits of distributed RAM and 64k bits of flash memory. All of this adds up to make quite a powerful device. A summary of the MACHXO2 family is here: http://www.latticesemi.com/documents/38834.pdf
The MACHXO2 series of devices can be considered to be either. Lattice, the manufacturer, lists it in both sections.
CPLD (Complex Programmable Logic Devices) started life as very simple PAL (Programmable Array Logic) devices, for example the PAL16L8. These were One Time Programmable (OTP) parts with a simple AND-OR-INVERT array and used a variety of manufacturer specific programming languages. Later, a re-programmable version was introduced and the designs became more complex, eventually morphing into CPLD devices.
FPGA (Field Programmable Gate Array) designs approached from the other direction, taking the design elements of ASIC (Application Specific Integrated Circuits) and changing the metal layer interconnects into a memory structure. This resulted in devices whose characteristics could be changed after the silicon manufacturing stage, hence "Field Programmable".
Many FPGA devices require an external memory, such as an EEPROM, which is used to load the code into the FPGA every time it is powered. This adds complexity to the circuit but allows very large (and expensive!) devices to be made. CPLD devices usually incorporate the equivalent EEPROM within the same silicon, and the device self-loads on power-up. This limits the maximum practical logic content of a CPLD but makes it easier (and less expensive!) to integrate.
Over the years, FPGA and CPLD device functions have begun to overlap, and there is a somewhat fuzzy area where either description can be used. For the MACHXO2 series, as used in this project, the programming language is exactly the same as is used for the very large FPGA types, so the distinction is academic.
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