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A low-cost, open source USB 3.0 Software Defined Radio platform with many examples and tutorials to help you experiment with RF.
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501 backers pledged $191,422 to help bring this project to life.

Thank you!

Thank you everyone for the tremendous amount of support you have shown for the bladeRF! It has been amazing to see our initial goal being reached in less than 8 days. Along the way we have been featured by HackadaySlashdot, and mentioned by some very inspiring people via Twitter! We were taken by surprise by the enthusiasm we have seen from the community, so to keep things interesting we will be announcing several stretch goals very soon!

Having reached our initial goal so quickly, we can get a head start on the pre-production run of the bladeRF. This extra time will give us much more time to consider and integrate backer requested features, so please don't hesitate to use the comments page!

Thanks again everyone!


    1. Creator Nuand on February 8, 2013

      Along with a few other requests for more GPIO, the board is getting a little crowded. As a solution, would a design where the SMB port on the board is routed to a clock pin on the FPGA work for you? I think a way can be easily worked out so you have the same sampling reference clock across multiple boards, thus allowing a MIMO configuration.
      Is there a specific PLL chip you have in mind? Is there a specific jitter or other requirement you want to achieve?

    2. Creator Paul L. Oxley on February 6, 2013

      The RASDR team (including Bogdan and myself) would like to see a SMA or SMB jack that could be used to supply a reference frequency(i.e. 10 MHz) to one of the GPIO pins. It should be equipped with a 50 ohm terminating resistor for impedance matching. This would allow more accurate frequencies in the system, thus making it more attractive for Radio Astronomy. This would also require some firmware development that Bogdan might be willing to undertake. The firmware would provide the PLL function to lock the TCVCXO to the reference via the DAC/spi link. On the Lime evaluation board that we have been using, the reference frequency lock is provided by a ADF PLL chip. This alternative would also be suitable, but likely more costly. Our current software operating on Windows can set the N & R counter values in the ADF to acheive a lock.